Method for fabrication of semiconductor device

ABSTRACT

An object of the invention is to prevent the occurrence of breaking or short-circuiting of a wiring caused by a difference in level in an isolation trench area formed in an SOI substrate. An oxide film is formed for a pad on the main surface of an SOI layer formed on an insulating substrate, a silicon nitride film are formed and an SiO 2  film in order, then an isolation trench reaching to the insulating substrate is by means of an R.I.E process using the SiO 2  film as a mask. Thereafter an insulating film is formed on an inside wall of the isolation trench by means of thermal oxidation, the isolation trench is filled with polysilicon, the polysilicon is etched back while controlling the etching so that the top of the polysilicon in the isolation trench remains higher than the top of the silicon nitride film, an extra part of the polysilicon deposited on the surface of the substrate, is removed and then the SiO 2  film used as a mask when forming the isolation trench is etched off using the polysilicon in the isolation trench and the silicon nitride film as an etching stopper. In this manner, since the SiO 2  film used as a mask is etched off after filling the isolation trench with polysilicon, the oxide film for isolating between the substrates is not etched when removing the mask film. Moreover since the polysilicon is the isolation trench and the silicon nitride film act as an etching stopper when etching off the SiO 2  film used as a mask, the oxide film for a pad existing thereunder and the insulating film formed on an inside wall of the trench can also be prevented from being etched and a flatness at an isolation trench area is not deteriorated.

TECHNICAL FIELD

The present invention relates to a method for fabrication of asemiconductor device and particularly to a manufacturing methodpreferred for isolating elements from each other by forming a deeptrench on a silicon substrate.

BACKGROUND ART

Up to now a method for isolating respective elements from each other bymeans of an insulator has been known as a element isolating method usedin a monolithic semiconductor integrated circuit.

In the Japanese patent Application Laid Open No. 59852-1986, forexample, a semiconductor device manufacturing method of isolatingelements from each other by forming an isolation trench on a bonded SOI(silicon on insulator) substrate is disclosed. This method is the onewhich makes an SOI substrate by bonding a silicon substrate 42 withanother silicon substrate 40 on which surface an insulating film 41 isformed as shown in FIG. 36(A) through an insulating film 41 as shown inFIG. 36(B), forms isolation trenches 43 reaching to the insulating film41 in the SOI substrate from one main surface of this SOI substrate,then forms an insulating film 44 on the surface of the SOI substrateincluding inside walls of the isolation trench 43 by thermal oxidationor the like as shown in FIG. 36(C), fills the isolation trenches 43 withpolysilicon 45 as shown in FIG. 36(D), removes extra parts of theinsulating film 44 and polysilicon 45 which comes out from the isolationtrenches 43, and electrically completely isolates respective elementareas 46 from the substrate 40 or from each other by means of aninsulator as shown FIG. 36(E).

As disclosed on page 66 of a reference paper "Ultra-Fast Silicon BipolarTechnology", for example, a method for forming an isolation trench forisolating respective elements from each other after forming a fieldoxide film which has a thick portion and a thin portion on the mainsurface of a silicon substrate is known as a method for forming anisolation trench. The method will be described in the following.

As shown in FIG. 37, the method forms one by one in order a partiallytrick field oxide film 32, a silicon nitride film 33 and a silicon oxidefilm to be used as a mask on the main surface of a silicon substrate 31,forms an opening by selectively etching the field oxide film 32, thesilicon nitride film 33 and the silicon oxide film 34 in an area wherethe field oxide film is thin in thickness, then forms an isolationtrench 35 by etching the silicon substrate 31 through the opening. Andit etches off the silicon oxide film 34 used as a mask, forms aninsulating film 36 on an inside wall of the isolation trench 35, thenfills polysilicon 37 in the isolation trench 35. Further, it performsetching back of the polysilicon 37 deposited on the silicon nitride film33 when filling the isolation trench with the polysilicon 37, etches offthe silicon nitride film 33, and then forms a silicon oxide film 38 onthe top of the polysilicon 37 in the isolation trench (see FIG. 38). Inthis manner, the method electrically divides completely the siliconsubstrate 31 into respective element areas by the isolation trench 35and the insulating film 36.

In a series of manufacturing treatments shown in FIG. 36(A) to 36(E), upto now as described above, an oxide film is generally formed on thesurface of an SOI substrate as a mask for forming an isolation trench onthe SOI substrate. And the oxide film used as the mask for forming anisolation trench has been removed at once after forming the isolationtrench. However as shown in FIG. 36(E), in case of isolating an elementarea 46 by insulating film 41 from a substrate 40, an insulating filmfor isolating from the substrate is exposed inside the isolation trenchimmediately after forming the isolation trench. In this case, since theinsulating film 41 inside the SOI substrate for isolating substrate andthe oxide film for the mask have about equal etching rate, so that, ifattempting to etch off the oxide film as the mask immediately afterforming the isolation trench, the insulating film inside the substratealso is etched off at the same time.

The present invention has been made by taking consideration of theabove-mentioned actual facts. The first object of the invention is toprovide a method for manufacturing a semiconductor device which makes itpossible to prevent a local deterioration of dielectric strength in anisolation trench area by protecting the insulating film for isolatingbetween the substrates which is exposed inside the isolation trenchesfrom being etched in the course of the treatment.

The reason why an isolation trench is formed in an area where a fieldoxide film is thin in thickness as shown in FIG. 37 is thatdeterioration of flatness of the surface of a substrate is preventedwhich is feared in case of forming the isolation trench in an area wherethe field oxide film is thick in thickness. In case of forming anisolation trench in an area where a field oxide film is thick, an endface of the field oxide film is largely exposed by the isolation trench,the field oxide film also is etched when etching off a silicon oxidefilm used as a mask, and a deep hollow is caused to deteriorate flatnessof the substrate. Deterioration of flatness of the substrate causes sucha problem as breaking and short-circuiting of a polysilicon wiring oraluminum wiring. Therefore, if an isolation trench is formed in an areawhere a field oxide film is thin in thickness, deterioration of flatnessof the substrate does not cause much of a problem even if the fieldoxide film is etched.

On the other hand, in case of forming an isolation trench in an areawhere a field oxide film is thin after forming the field oxide film asin a former method shown in FIGS. 37 and 38, it is necessary to make asemiconductor device for example a transistor to be manufactured largerin size by allowing for some divergence in mask matching so as to surelyprevent trouble due to exposing the end face of a thick part of thefield oxide film by an isolation trench.

The second object of the invention is to prevent a semiconductor devicefrom being made unnecessarily large in size without deterioratingflatness of the surface of a substrate even if forming an isolationtrench in an area where a field oxide film is thick by takingconsideration of the above-mentioned problems.

An isolation trench as described above is generally formed by etching asilicon substrate through the R.I.E (reactive ion etching) process. TheR.I.E process is a process in which a cathode fall voltage (biasvoltage) is generated by applying a high frequency voltage to anelectrode on which a silicon substrate is mounted and the siliconsubstrate is etched by having ions or radicals as active particlesgenerated by being plasma discharged material gas of a fluoride seriescollide and react against the substrate. Since the R.I.E process beingaccompanied by a physical etching action is greatly aggressive to thesilicon substrate, it caues crystal defects on the surface of insidewalls of an isolation trench and the surface of the silicon substratesurrounding the inside walls cause leakage of electric current due tothe etching damage. For the purpose of eliminating such crystal defects,up to now an inside wall of an isolation trench has been processed bymeans of a sacrifice oxidation process or C,D,E (chemical dry etching)process, as disclosed in Japanese patent Applications Laid Open No.127850-1991 and No. 129854-1991, for example. The sacrifice oxidationprocess is a process of eliminating crystal defects by etching off anoxide film after forming the oxide film reaching to a depth wherecrystal defects exist in inside walls of an isolation trench. And theC.D.E process is a process of etching off a part having crystal defectsby only a less aggresive chemical etching by means of radicals ofmaterial gas activated by plasma discharge.

DISCLOSURE OF INVENTION

To attain the first object of the invention, a method of the inventionfills in an isolation trench with polysilicon, removes an extra part ofthe polysilicon protruded out from the isolation trench on thesubstrate, and then etches off an oxide film as a mark.

Namely, a method of the invention deposits a layer for a mask on themain surface of a semiconductor substrate, makes an opening for exposinga specified part of the main surface of the semiconductor substrate inthe layer for a mask, forms a groove by etching the semiconductorsubstrate through the opening by making the layer for a mask as a mask,forms an insulating film on the surface of inside walls of the groove,fills in the groove with a filler through the opening, removes an extrapart of the filler deposited on the surface of the layer for a mask toexpose the layer for a mask, and then removes the layer for a mask.

In particular, in case of isolating an SOI area, a method of theinvention comprises:

a step of depositing a layer for a mask on the main surface of an SOIlayer set on an insulating substrate,

a step of making an opening in the layer for a mask to expose aspecified part of the main surface of the SOI layer,

a step of forming an isolation trench reaching to the insulatingsubstrate by etching the SOI layer through the opening by making thelayer for a mask as a mask.

a step of forming an insulating film on the surface of inside walls ofthe isolation trench,

a step of filling in the isolation trench with a filler through theopening,

a step of removing an extra part of the filler deposited on the surfaceof the layer for a mask to expose the layer for a mask, and

a step of removing the mask layer.

Since the mask layer for forming a groove is removed after the groove isfilled with a filler and an extra part of the filler protruded out ontothe surface of the substrate from the groove is removed, a method of theinvention in case of isolating by insulating an SOI area can preventetching of an insulating film to isolate between the substrates which isexposed inside the isolation trench in the course of the above-mentionedtreatment and can prevent local deterioration of dielectric strength inthe isolation trench.

To attain the second object of the invention, a method of the inventionforms a layer as an etch deterring film in advance under a layer used asa mask in case of forming a groove, and removes the layer for a mask ina state where the etch deterring layer contacts with a filler filled inthe groove.

Namely, a method of the invention deposits one by one in order a firstlayer (layer of an etch deterring film) and a second layer (layer usedas a mask in forming a groove), makes an opening for exposing aspecified part of the main surface of the semiconductor substrate on thefirst and second layers, makes a groove by etching the semiconductorsubstrate through the opening by making the second layer as a mask,forms an insulating film on the surface of inside walls of the trench,fills in the groove with a filler through the opening until the top ofthe filler comes to be equal to or higher than the first layer inheight, and removes the second layer by making the filler and the firstlayer as an etching stopper.

In particular, in case of performing isolation of an SOI area a methodof the invention comprises:

a step of depositing one by one in order a first layer and a secondlayer on the main surface of an SOI layer set on an insulatingsubstrate,

a step of making an opening in the first and second layers to expose aspecified part of the main surface of the SOI layer,

a step of forming an isolation trench reaching to the insulatingsubstrate by etching the SOI layer through the opening by making thesecond layer as a mask,

a step of forming an insulating film on the surface of inside walls ofthe isolation trench,

a step of filling in the isolation trench with a filler through theopening until the top of the filler comes to be equal to or higher inheight than the first layer, and

a step of removing the second layer by making the filler and the firstlayer as an etching stopper.

In this manner, a semiconductor device manufacturing method of theinvention forms the first and second layers one by one in order on themain surface of a substrate and controls the top of the filler to befilled in a groove so as to come to be equal to or higher than the firstlayer in height. Therefore, when etching off the second layer used as amask in forming the groove, the filler and the first layer preventproceeding of etching to a layer lower than them, so that, for example,a difference in level in a trench area caused by etching of a fieldoxide film and the like formed on the surface of a semiconductorsubstrate and the like does not appear.

According to the invention, therefore, even if an isolation trench isformed in an area where a field oxide film is thick, flatness of thesurface of a substrate is not deteriorated and unnecessary magnificationin size of a semiconductor device up to now caused by expecting somedivergence in mask matching can also be prevented.

And when removing the second layer used as a mask, not only a fieldoxide film but also an insulating film formed on the surface of insidewalls of the groove are not etched in the direction of depth. If theinsulating film on the surface of the inside walls of the groove isetched, a sharp difference in level is formed on the surface of thesubstrate in an area of the trench and causes a problem of breaking orshort-circuiting of a polysilicon wiring or aluminum wiring on thesurface of the substrate, but if the invention is applied, since adifference in level does not appear on the trench area and the surfaceof the substrate can be flat, it is made possible to manufacture asemiconductor device having no breaking or short-circuiting of apolysilicon wiring or aluminum wiring.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 to 13 are cross-sectional views of an SOI substrate forexplaining in order manufacturing process of the SOI substrate in caseof applying a manufacturing method of a first embodiment of theinvention.

FIGS. 14 to 17 are cross-sectional views of an SOI substrate forexplaining in order manufacturing processes of the SOI substrate in caseof applying a manufacturing method of a second embodiment of theinvention.

FIG. 18 is a diagram for showing a result of measuring density ofdefects after forming an isolation trench.

FIGS. 19 to 31 are cross-sectional views of an SOI substrate forexplaining in order manufacturing processes of the SOI substrate in caseof applying a manufacturing method of a third embodiment of theinvention.

FIGS. 32 to 35 are cross-sectional views of an SOI substrate forexplaining in order manufacturing processes of the SOI substrate in caseof applying a manufacturing method of a fourth embodiment of theinvention.

FIGS. 36(A) to 36(E) are cross-sectional views of an SOI substrate forexplaining in order former manufacturing processes of the SOI substrate.

FIGS. 37 an 38 are cross-sectional views of a substrate for explaining aformer treatment of forming a trench.

DESCRIPTION OF PREFERRED EMBODIMENTS

Embodiments of the invention will be described in the following withreference to the drawings.

THE FIRST EMBODIMENT

The first embodiment of the invention applies a final polishing to onemain surface of a first P⁻ type single crystal silicon substrate 1 andthen forms an insulating film 2 of specified thickness on it by thermaloxidation. And the embodiment bonds a second single crystal siliconsubstrate 3 having the finally-polished main surfaces performedmirror-like polishing to the insulating film 2 side of the surface ofthe first silicon substrate 1 under a sufficiently clean atmosphere andheats them to bond them as one so as to hold the insulating film 2between the respective silicon substrates 1 and 3. In this manner, anSOI substrate is made which is composed by bonding the second substrate3 through the insulating film 2 on the first silicon substrate 1 (seeFIG. 1). In FIG. 1, a reference number 4 shows and N type high-densityimpurity (Sb) layer made by doping from the surface of the second N⁻type silicon substrate 3 before performing the bonding.

And the embodiment forms a pad oxide film 8a on the surface of thesecond silicon substrate 3 side by thermal oxidation, deposits one byone in order on this surface an Si₃ N₄ film 9 as a first insulatinglayer and an SiO₂ film 10 as a second insulating film by a CVD method,and anneals the substrate at 1000° C. to make the SiO₂ film 10 closely,and then deposits an unshown photoresist on it, processes it by means ofa publicly known photolithography process and R.I.E process using a gasof CF₄ or CHF₃ series as an etching gas, and makes an opening 11 byselectively etching the SiO₂ film 10, Si₃ N₄ film 9 and pad oxide film8a up to reaching to the surface of the silicon substrate 3 using thephotoresist deposited on the surface of the SiO₂ film 10 as a mask (seeFIG. 2). FIG. 2 shows a state after stripping off the photoresist.

Next, the embodiment makes an isolation trench 12 reaching up to theinsulating film 2 by selectively etching the second silicon substrate 3using the SiO₂ film as a mask by means of an R.I.E process using a gasof HBr series as an etching gas (see FIG. 3). In this case, thethickness of the SiO₂ film 10 to be deposited has been determined in theprevious step so that the isolation trench 12 may successfully reach tothe insulating film 2 according by the etching rates of the SiO₂ filmand the silicon substrate 3.

Next, a C.D.E treatment is applied to the surface of the inside walls ofthe isolation trench 12. The C.D.E treatment is performed using an RFdischarge type plasma etching system under a condition, for example, ofmaterial gases of CF₄, O₂ and N₂, a discharge frequency of 13.56 MHz, anetching rate of 1500 Å/min, and a distance from plasma to the wafer of100 cm. In this manner, the inside wall of the isolation trench 12 isetched by about 1500 Å.

Next, the inside walls of the isolation trench 12 processed in the C.D.Etreatment are annealed. The annealing process is performed, for example,by heating for 30 minutes at 1000° C. in an atmosphere of N₂.

Next, a sacrifice oxidation process may be applied to the annealedinside walls of the isolation trench 12, the sacrifice oxidation processis performed, for example, by forming a sacrifice oxide film of 500 Å bymeans of a dry oxidation process at 1000° C. and then removing thissacrifice oxide film by fluoric acid.

And an insulating film 13 is formed on the inside walls of the isolationtrench 12 by means of a wet thermal oxidation at 1050° C., for example,and then polysilicon 14 is deposited on it by means of an LP-CVD method.At this time, the polysilicon not only fills the isolation trench 12 butalso deposits on the SiO₂ film 10 (see FIG. 4).

Next, an extra part of the polysilicon 14 deposited on the SiO₂ film 10is subjected to etching back (the first time) by means of a dry etchingmethod (see FIG. 5). At this time, the etching process is stopped sothat the top of the polysilicon 14 remaining in the isolation trench 12is higher than the Si₃ N₄ film 9.

Next, the SiO₂ film 10 is etched off by means of a wet etching methodusing a fluorine solution (see FIG. 6). In this case, since the Si₃ N₄film 9 and the polysilicon 14 left so that its top is higher than theSi₃ N₄ film 9 act as an etching stopper, the pad oxide film 8a and theinsulating film 13 formed on the inside walls of the isolation trench 12are not etched.

Next, the part of the polysilicon 14 filled in the isolation trench 12projecting beyond the Si₃ N₄ film 9 is etched back by dry etching (thesecond time) (see FIG. 7). In this case, it is desirable to control thetop of the polysilicon 14 to come to be about 0.3 μm lower than the topof the pad oxide film 8a so that a thermal oxide film 15 may come to beon a same level with the surrounding pad oxide film 8a when having hadthe thermal oxide film 15 grow on the polysilicon 14 in the next step aswill be described.

Next, after the oxide film 15 has been grown by selectively thermallyoxidizing the top of the polysilicon 14 filled in the isolation trench12 through an opening of the Si₃ N₄ film 9 (see FIG. 8), the Si₃ N₄ film9 is etched off (see FIG. 9). As is clearly shown in FIG. 9, an area ofthe isolation trench 12 is kept flat without forming a difference inlevel.

A P well region 5, an N well region 6a and deep N⁺ region 7 are formedin the second silicon substrate 3 side made into an SOI layer by meansof a publicly known photolithography process and impurity diffusionprocess (see FIG. 10).

After this, a field oxide film 8 is formed on the surface of the secondsilicon substrate 3 side by means of LOCOS (local oxidation of silicon)method (see FIG. 11). The LOCOS method is a process which forms again anSi₃ N₄ film as an oxidation deterring film on a specified part of asubstrate and then forms a thick field oxide film 8 by oxidizing a partwhere the Si₃ N₄ film is not formed by means of thermal oxidation or thelike. FIG. 11 shows a state after removing the Si₃ N₄ film by H₃ PO₄after performing oxidization by means of the LOCOS method.

Next, the process of the embodiment forms a thin gate film afterremoving a pad oxide film 8a, forms a polysilicon wiring (gateelectrode) 16 by applying an LP-CVD method, a photolithography processand an etching method, and forms a P⁺ diffusion layer 17 and an N⁺diffusion layer 18 by means of selective doping (see FIG. 12). Duringthis process, since an etched depth of the field oxide film 8 is about0.2 μm, a flatness of the isolation trench 12 area is not deteriorated.

After this, the process deposits an interlayer insulating film 19 ofPSG, BPSG or the like, makes a contact hole in a necessary part, andforms an aluminum wiring 20 and a passivation film 21 made of a nitridefilm or the like by means of plasma CVD method, and thus manufactures aBi-CMOS semiconductor device in which a CMOS transistor and a bipolartransistor are composited (see FIG. 13).

In this manner, a manufacturing method of the invention preventsproceeding of etching to the pad oxide film 8a or an insulating film 13and the like which exist under the Si₃ N₄ film 9 and the polysilicon 14when etching off the SiO₂ film 10 in the parts of isolation trench 12area. Therefore, since flatness of the isolation trench 12 area can beobtained without making difference in level, such a problem as breakingor short-circuiting of a polysilicon wiring 16 or aluminum wiring 20 isnot caused.

And since the embodiment performs C.D.E treatment and annealing processafter forming an isolation trench, it can prevent crystal defects whichhave been inevitably generated on the inside walls of the isolationtrench and its surrounding surface of the silicon substrate when formingthe isolation trench. This will be described in detail in the following.

In the above-mentioned embodiment, after an insulating film 13 wasformed on the inside walls of the isolation trench 12, the insulatingfilm 13, SiO₂ film 8a and Si₃ N₄ film 9 were etched off, crystal defectswere revealed by means of a secco etching process, and the surface ofthe second silicon substrate 3 was observed by means of an opticalmicroscope. And density of defects was computed by counting defectsobserved within a square of which one side is 200 μm. The result isshown in FIG. 18.

For comparison, density of defects was examined in the same manner alsofor ones which were processed neither C.D.E treatment nor annealingprocess, only an annealing process, an annealing process and a sacrificeoxidation process, only a C.D.E treatment, a C.D.E treatment and asacrifice oxidation process, and a C.D.E treatment and an annealingprocess. The result is also shown in FIG. 18. In FIG. 18, a curveplotted by points+shows a result of observing the middle part of thesurface of the second silicon substrate 3, a curve plotted by □shows aresult of observing the upper part of the surface of the second siliconsubstrate 3, and a curve plotted by Δ shows a result of observing thelower part of the surface of the second silicon substrate 3.

As the result, in the substrates which were processed by means ofneither C.D.E treatment nor annealing process and by means of only oneof them, reduction in density of defects was not seen, but crystaldefects were observed in the vicinity of the isolation trench 12 on thesurface of the second silicon substrate 3. Namely, it has been provedthat a former method performing only a sacrifice oxidation process and aC.D.E treatment cannot completely prevent crystal defects and cannotfully solve the troubles caused by crystal defects. On the other hand,crystal defects could be prevented in both substrates which wereprocessed respectively by means of a C.D.E treatment and an annealingprocess and by means of a C.D.E treatment, an annealing process and asacrifice oxidation process. As the result, it can be confirmed that itis possible to prevent crystal defects by applying at least a C.D.Etreatment and an annealing process. FIG. 18 shows that the density ofdefects of them is 10₄ defects/cm², but this value is brought from themeasurement limit and actually any crystal defects have not beenobserved. The above-mentioned measurement of density of defects was madeby observing only the surface of the second silicon substrate 3, but asa result of observing a cross section of the second silicon substrate 3,a method of the embodiment could prevent crystal defects in the insidewalls of the isolation trench also.

In this way, damaged layers generated on an inside wall of a groove andon the surface of a silicon substrate in the vicinity of the groove whenforming the groove are fully removed by process C.D.E treatment to theinside wall of the groove in the silicon substrate. And a damaged layerwhich has not completely been removed by the C.D.E process and anotherdamaged layer newly generated by the C.D.E treatment are recovered byannealing the inside wall of the groove. In this manner, it is possibleto eliminate crystal defects which have been inevitably generated on aninside wall of a groove and on the surface of a silicon substrate in thevicinity of the groove when forming the trench and to prevent thetroubles of current leakage caused by crystal defects.

A condition of the C.D.E treatment is not particularly limited, but itis desirable to be a condition for making it possible to completely etchoff a damaged layer generated when forming a groove, and furthermorewhich can suppress to the utmost a new damaged layer from beinggenerated by the C.D.E process. This C.D.E treatment etches off thesubstrate to a depth of twice to 5 times of the damaged layer generatedwhen forming the groove.

And a condition of the annealing is not particularly limited so long asit can recover a damaged layer which has not completely removed by aC.D.E treatment and another damaged layer newly generated by a C.D.Eprocess, but it can be done, for example, in a condition of heating for10 to 30 minutes at 1000° to 1100° C. in an atmosphere of inactive N₂.

In the above-mentioned first embodiment, a first etching-back treatmentof the polysilicon 14 is performed by a dry etching process, but it maybe performed by polishing.

THE SECOND EMBODIMENT

A second embodiment using a polysilicon film 9' instead of an Si₃ N₄film 9 in the above-mentioned first embodiment is described in thefollowing.

The present embodiment gets an SOI substrate shown in FIG. 1 asmentioned above, forms a pad oxide film 8a on the substrate as describedabove, deposits in order a polysilicon film 9' by means of LP-CVD methodand an SiO₂ film 10 by means of a CVD method, and anneals the substrateat 1000° C. to make the SiO₂ film 10 closely in the same manner as shownin FIG. 2. After this, the embodiment deposits a photoresist on thesubstrate, makes a photoresist pattern by means of photolithographytreatment, makes an opening 11 in the SiO₂ film 10, the polysilicon film9' and the pad oxide film 8a by means of R.I.E treatment using a gas ofCF₄ or CHF₃ series as an etching gas, and deposits a Si₃ N₄ film 22 onthe surface of the substrate (see FIG. 14). The substrate is thenprocessed by means of an anisotropic R.I.E treatment which leaves theSi₃ N₄ film 22 only on the side wall of the opening 11 (see FIG. 15).The Si₃ N₄ film 22 prevents the polysilicon film 9' exposed inside theopening 11 from being oxidized at the same time as when an insulatingfilm 13 is formed on an inside wall of the isolation trench 12 by meansof thermal oxidation in the following step.

Next, the embodiment selectively etches the second silicon substrate 3using the SiO₂ film as a mask by means of an R.I.E process using a gasof HBr series as an etching gas to make an isolation trench 12 reachingup to the insulating film 2, and processes the inside walls of theisolation trench 12 by means of a C.D.E treatment and an annealingprocess in order, as described above. And an insulating film 13 isformed by thermally oxidizing the inside walls of the isolation trench12 and then the Si₃ N₄ film 22 covering the wall of the opening 11 isremoved by a H₃ PO₄ solution (see FIG. 16). As described above, in caseof forming the insulating film 13, the polysilicon film 9' is notoxidized, since it is covered by the Si₃ N₄ film 22 in the opening 11.If the polysilicon film 9' is oxidized at this time, the oxidized partof the polysilicon film 9' also comes to be etched by etchant at thesame time as when etching off the SiO₂ film 10 in the following step,and this causes a difference in level in the isolation trench 12 area.

Next, in the same manner as the step shown in FIG. 4, after depositingthe polysilicon 14 (see FIG. 17), by passing through the same steps asshown in FIGS. 5 to 13, a Bi-CMOS semiconductor device is manufactured.

In the present embodiment, since the polysilicon film 9' and thepolysilicon 14 filled in the isolation trench 12 act as an etchingstopper when removing the SiO₂ film 10, it is prevented that the padoxide film 8a under the polysilicon film 9' and the insulating film 13are etched at the same time. And as described above, since there is notan oxidized part also in the polysilicon film 9', etching does notproceed to a lower layer thereunder.

Furthermore, the second embodiment can remove the polysilicon film 9' atthe same time as when applying the second etching-back process to thepolysilicon film 14.

THE THIRD EMBODIMENT

The above-mentioned first embodiment forms a pad silicon oxide film ofuniform thickness, forms an isolation trench after deposition of an Si₃N₄ film and an SiO₂ film by means of a CVD method, performs in orderforming an insulating film on the inside wall of the isolation trench,filling the isolation trench with polysilicon, etching back an extrapart of the polysilicon, and etching off the SiO₂ film using the Si₃ N₄film and the polysilicon as an etching stopper, performs patterning ofthe Si₃ N₄ film or redepositing of the Si₃ N₄ film, and then forms afield oxide film by processing the pad silicon oxide film by means of anLOCOS process, but the field oxide film 8 may be formed by means of anLOCOS process in advance. An example of it is shown in the thirdembodiment.

The third embodiment of the invention applies a mirror-like polishing toone main surface of a first P⁻ type single crystal silicon substrate 1and then forms an insulating film 2 of specified thickness on it bymeans of thermal oxidation. And the third embodiment bonds a secondsingle crystal silicon substrate 3 having a mirror-like polished mainsurfaces to the insulating film 2 side of the surface of the firstsilicon substrate 1 and heats them as a sufficiently clean atmosphere tobond them in one so as to hold the insulating film 2 between therespective silicon substrates 1 and 3. In this manner, an SOI substrateis made which is composed by bonding the second silicon substrate 3through the insulating film 2 to the first silicon substrate 1 (see FIG.19). In FIG. 19, a reference number 4 shows an N type high-densityimpurity (Sb) layer made by doping from the surface of the second N⁻type silicon substrate 3 before bonding of the two substrates.

And the embodiment forms a P well region 5, N well region 6 and deep N⁺region 7 on the second silicon substrate 3 side made into an SOI layerby means of a series of oxidation, photolithography and impuritydiffusion process (see FIG. 20). During this process, an oxide film onthe surface of the second silicon substrate 3 can be freely grown andremoved.

After this, a field oxide film 8 is formed on the surface of the secondsilicon substrate 3 side by means of a LOCOS method (see FIG. 21). FIG.21 shows a state after removing an Si₃ N₄ film with H₃ PO₄ afterperforming oxidation by means of an LOCOS process.

And the third embodiment deposits again in order an Si₃ N₄ film 9 as afirst insulating layer and an SiO₂ film 10 as a second insulating layeron the surface of the substrate by means of a CVD process, and annealsthem at 1000° C. to make the SiO₂ film 10 closely. Next, the embodimentdeposits an unshown photoresist and in an area where the field oxidefilm 8 is thick in thickness the embodiment makes an opening 11 reachingto the surface of the silicon substrate 3 by selectively etching theSiO₂ film 10, Si₃ N₄ film 9 and field oxide film 8 using the photoresistas a mask by means of a publicly known photolithography process andR.I.E process using a gas of CF₄ or CHF₃ series as an etching gas (seeFIG. 22). FIG. 22 shows a state after stripping off the photoresist.

Next, the embodiment makes an isolation trench 12 reaching to theinsulating film 2 by selectively etching the second silicon substrate 3using the SiO₂ film 10 as a mask by means of an RIE process using a gasof HBr series as an etching gas film 2 (see FIG. 23). In this case, thethickness of the SiO₂ film 10 to be deposited in the previous step hasbeen determined so that the isolation trench 12 may successfully reachto the insulating film 2 by the etching rates of the SiO₂ film 10 andthe silicon substrate 3.

Next, a C.D.E treatment is applied to the surface of the inside walls ofthe isolation trench 12. This C.D.E treatment is performed by means ofan RF discharge type plasma etching apparatus under a condition, forexample, of material gases of CF₄, O₂ and N₂, a discharge frequency of13.56 MHz, an etching rate of 1500 Å/min, and a distance from the plasmato the wafer of 100 cm. In this manner, the inside walls of theisolation trench 12 are etched by about 1500 Å.

Next, the inside walls of the isolation trench 12 in the C.D.E treatmentare annealed. This annealing process is performed, for example, byheating for 30 minutes at 1000° C. in an atmosphere of N₂.

Next, a sacrifice oxidation process may be applied to the annealedinside walls of the isolation trench 12. In this sacrifice oxidationprocess, for example, after forming a sacrifice oxide film of 500 Å bymeans of a dry oxidation process at 1000° C., then this sacrifice oxidefilm is removed by fluoric acid.

And an insulating film 13 is formed on the inside walls of the isolationtrench 12 by means of a wet thermal oxidation at 1050° C., for example,and then polysilicon 14 is deposited on it by means of an LP-CVD method.At this time, the polysilicon 14 not only fills the isolation trench 12but also deposits on the SiO₂ film 10 (see FIG. 24).

Next, the polysilicon 14 deposited on the SiO₂ film 10 by dry etchingprocess is etched back (the first time) (see FIG. 25). At this time, theetching process is stopped so that the top of the polysilicon 14remaining in the isolation trench 12 is higher than the Si₃ N₄ film 9.

Next, the SiO₂ film 10 is etched off by means of a wet etching processusing a fluorine solution (see FIG. 26). In this case, since the Si₃ N₄film 9 and the polysilicon 14 left so that its top portion is higherthan the Si₃ N₄ film 9 acts as an etching stopper, the field oxide film8 under the Si₃ N₄ film 9 and the insulating film 13 formed on theinside walls of the isolation trench 12 are not etched.

Next, the part of the polysilicon 14 filled in the isolation trench 12which projects beyond the Si₃ N₄ film 9 is etched back (the second time)(see FIG. 27). In this case, it is desirable to control the top of thepolysilicon 14 to come to be 0.3 μm lower than the top of the fieldoxide film 8 so that a thermal oxide film 15 may come to be on a samelevel with the surrounding field oxide film 8 when growing the thermaloxide film 15 which will be described later on the polysilicon 14 in thenext step.

Next, after the oxide film 15 has been grown by thermally oxidizing thetop of the polysilicon 14 filled in the isolation trench 12 by the Si₃N₄ film 9 (see FIG. 28), the Si₃ N₄ film 9 is etched off (see FIG. 29).As is clearly shown in FIG. 29, an area of the isolation trench 12 iskept flat without making a difference in level.

And the third embodiment forms a thin gate oxide film after removing apad oxide film 8a, then forms a polysilicon wiring (gate electrode) 16by means of an LP-CVD method, photolithography process and etchingprocess, and forms a P⁺ diffusion layer 17 and N⁺ diffusion layer 18 bymeans of selective doping (see FIG. 30). During this process, since anetching depth of the field oxide film 8 is about 0.2 μm, a flatness ofthe isolation trench 12 area is not deteriorated.

After this, the present embodiment deposits an interlayer insulatingfilm 19 of PSG, BPSG or the like, makes a contact hole in a necessarypart, and forms an aluminum wiring 20 and a passivation film 21 made ofa nitride film or the like by means of a plasma CVD method, and thusmanufactures a Bi-CMOS semiconductor device in which a CMOS transistorand a bipolar transistor are composited (see FIG. 31).

In this manner, a manufacturing method of the invention prevents theproceeding of etching for an oxide film such as a field oxide film 8 oran insulating film 13 and the like which exist under the Si₃ N₄ film 9and the polysilicon 14 when etching off the SiO₂ film 10 in theisolation trench 12 area. Therefore, since flatness of the isolationtrench 12 area can be obtained without making difference in level, suchtroubles as breaking or short-circuiting of a polysilicon wiring 16 oraluminum wiring 20 is not caused.

And in the above-mentioned former method shown in FIGS. 37 and 38, sincean isolation trench 35 is formed in an area where an field oxide film 32is thin in thickness, a edge part B of the silicon substrate 31 existsaround the top of the isolation trench 35, so the etched-back top of thepolysilicon 37 comes to be lower than the edge part B. Therefore, avertical bird's beak A comes to be formed in a corner when forming anoxide film 38 on the top of the polysilicon 37 and as a result a problemhas been brought that crystal defects are liable to be generated bystress concentration to the edge part B of the silicon substrate 31.

In the present embodiment, since an isolation trench is formed in anarea where a field oxide film 8 is thick in thickness and the top of thepolysilicon 14 which has performed the second etching-back process comesto be higher than the top of the second silicon substrate 3 (see FIG.27), crystal defects are not generated when oxidizing the polysilicon 14without stress concentration to the second silicon substrate 3 caused bya vertical bird's beak as formed in a former method which forms anisolation trench in an area where a field oxide film 8 is thin inthickness (see FIGS. 37 and 38). Therefore, leakage of current caused bycrystal defects can be prevented. Furthermore, in opposition to theformer method which forms an isolation trench in an area where a fieldoxide film 8 is thin in thickness, the present embodiment does not needto make a semiconductor larger in size for the allowance for somedivergence in mask matching, so it can make the semiconductor devicesmaller in size.

In this manner, the embodiment makes it possible to form an isolationtrench in an area where a field oxide film is thick in thickness withoutdeteriorating flatness of a silicon substrate. Therefore, since it isnot necessary to allow for some divergence in mask matching andoccurrence of crystal defects of a silicon substrate is also deterred, asemiconductor device can be manufactured which does not have breaking orshort-circuiting of a polysilicon wiring and aluminum wiring and is notmade unnecessarily large in size.

And since an isolation trench is formed after forming a field oxidefilm, it is thought that occurrence of crystal defects around theisolation trench can be deterred. Namely, if a field oxide film isformed after forming an isolation trench, it is feared that the volumeexpands when forming the field oxide film and crystal defects aregenerated by stress concentration to the boundary between a siliconsubstrate and an isolation trench, but the present embodiment does nothave such a fear.

Furthermore, the present embodiment also applies a C.D.E treatment andannealing process to an inside wall of the isolation trench 12. Thanksto this, the embodiment makes it possible to fully or completely removeby means of a C.D.E treatment a damaged layer generated on the insidewall of the isolation trench 12 when forming the isolation trench 12, toremove by means of the following annealing process the damaged layerwhich has not completely been removed by the C.D.E treatment and anotherdamaged layer newly generated by the C.D.E process, and elimination ofcrystal defects on the inside walls and the like of the isolation trench12 becomes possible.

In the above-mentioned third embodiment, the first process of etchingback the polysilicon 14 is performed by a dry etching process, but itmay be done by a polishing process.

THE FOURTH EMBODIMENT

The fourth embodiment using a polysilicon film 9' instead of an Si₃ N₄film 9 used in the third embodiment is described in the following.

After processing a substrate in the steps shown in FIGS. 19 to 21, thepresent embodiment deposits in order a polysilicon film 9' by means ofan LP-CVD method and an SiO₂ film 10 by means of a CVD method andanneals the substrate at 1000° C. in the same way as the process shownin FIG. 22 to make the SiO₂ film 10 closely. After this, the presentembodiment deposits a photoresist, forms a photoresist pattern by meansof a photolithography process, makes an opening 11 in the SiO₂ film 10,polysilicon film 9' and field oxide film 8 by means of an R.I.E processusing a gas of CF₄ or CHF₃ based as an etching gas, and deposits an Si₃N₄ film 22 on the surface of the substrate (see FIG. 32). And theembodiment leaves the Si₃ N₄ film 22 only on a side wall of the opening11 by means of an anisotropic R.I.E process (see FIG. 33). The Si₃ N₄film 22 prevents the polysilicon film 9' exposed in the opening 11 frombeing oxidized at the same time as when forming an insulating film 13 onan inside wall of the isolation trench 12 by thermal oxidation in thefollowing step.

Next, the embodiment selectively etches the second silicon substrate 3using the SiO₂ film 10 as a mask by means of an R.I.E process using agas of HBr series as an etching gas to form the isolation trench 12reaching to the insulating film 2, applies in order a C.D.E treatmentand an annealing process on the inside wall of the isolation trench 12as described above, and forms the insulating film 13 by means of thermaloxidation, and then removes the Si₃ N₄ film 22 covering the surface ofthe wall of the opening 11 by means of H₃ PO₄ solution (see FIG. 34). Asdescribed above, in case of forming the insulating film 13, thepolysilicon film 9' is not oxidized, since it is covered by the Si₃ N₄film 22 in the opening 11. If the polysilicon film 9' is oxidized atthis time, the oxidized part of the polysilicon film 9' also comes to beetched by an etchant at the same time as when etching off the SiO₂ film10 in the following step, and this causes a difference in level in theisolation trench area.

Next, in the same manner as the step shown in FIG. 24, after depositingthe polysilicon 14 (see FIG. 35), by passing through the same steps asshown in FIGS. 25 to 31, a Bi-CMOS semiconductor device shown in FIG. 31is manufactured.

In the present embodiment, since the polysilicon film 9' and thepolysilicon 14 filled in the isolation trench 12 act as an etchingstopper when etching off the SiO₂ film, it is prevented that the fieldoxide film 8 and the insulating film 13 under the polysilicon film 9'are etched at the same time. And as described above, since there is notan oxidized part also in the polysilicon film 9', the etching does notproceed to a lower layer from there.

Furthermore, the present fourth embodiment can remove the polysiliconfilm 9' at the same time as when applying the second etching-backprocess to the polysilicon film 14.

In the above-mentioned various embodiments, as an oxide film to be usedas a mask when forming an isolation trench, an SiO₂ film is formed bymeans of a CVD method, but PSG (phospho silicate glass) film also may beformed instead of the SiO₂ film.

And the above-mentioned various embodiments show examples of applyingthe invention to an isolation trench of an SOI substrate, but theinvention can be applied also to a trench capacitor and trench isolationof a simple silicon substrate.

INDUSTRIAL APPLICABILITY

According to a manufacturing method of the invention described above, aninsulating film in a groove, a field oxide film around the groove, orthe like can be prevented from being etched at the same time as whenetching off a film used as a mask when forming the groove. Therefore,such disadvantages as local reduction of dielectric strength in a groovearea, deterioration of flatness of the surface of a substrate in thegroove area, and the like are not brought about and a semiconductorsubstrate having a trench with high reliable in a wiring layer can besupplied, and the invention is very effective, for example, inmanufacturing an SOI substrate having an isolation trench.

What is claimed is:
 1. A method for manufacturing a semiconductor devicecomprising steps of:depositing a mask layer on a main surface of asemiconductor substrate; forming an opening in the mask layer exposing aportion of the main surface of the semiconductor substrate; forming agroove by etching the semiconductor substrate through the opening in themask layer; processing an inside wall of the groove by means of achemical dry etching process; annealing the inside wall of the grooveprocessed by the chemical dry etching process; forming an insulatingfilm on an inside wall of the groove; filling the groove with a fillerthrough the opening; exposing the mask layer by removing a portion ofthe filler deposited on the surface of the mask layer; and removing themask layer.
 2. A method for manufacturing a semiconductor device asdefined in claim 1, wherein the annealing process is a process ofheating the semiconductor substrate at about 1000° to 1100° C. in anatmosphere of inactive gas.
 3. A method for manufacturing asemiconductor device comprising steps of:depositing a mask layer on amain surface of an SOI layer set on an insulating substrate; forming anopening in the mask layer exposing a portion of the main surface of theSOI layer; forming an isolation trench reaching through to theinsulating substrate by etching the SOI layer through the opening in themask layer; processing an inside wall of the isolation trench by meansof a chemical dry etching process; annealing the inside wall of theisolation trench processed by the chemical dry etching process; formingan insulating film on an inside wall of the isolation trench; filling inthe isolation trench with a filler through the opening; exposing thelayer for a mask by removing an extra part of the filler deposited onthe surface of the mask layer; and removing the mask layer.
 4. A methodfor manufacturing a semiconductor device as defined in claim 3, whereinthe annealing process is a process of heating the semiconductorsubstrate at about 1000° to 1100° C. in an atmosphere of inactive gas.5. A method for manufacturing a semiconductor device comprising stepsof:depositing in order a first layer and a second layer on a mainsurface of a semiconductor substrate; forming an opening in the firstlayer and the second layer exposing a portion of the main surface of thesemiconductor substrate; forming a groove by etching the semiconductorsubstrate through the opening using the second layer as a mask; formingan insulating film on an inside wall of the groove, the insulating filmbeing a material different from a material of the first layer; fillingthe groove with a filler through the opening until a top surface of thefiller becomes equal to or higher than the first layer in height and sothat the filler contacts the first layer at the opening; and removingthe second layer using the filler filled to the height equal to orhigher than the first layer and the first layer as an etching stopper toprevent the insulating film located below a contact portion between thefirst layer and the filler from being etched during the removal of thesecond layer.
 6. A method for manufacturing a semiconductor device asdefined in claim 5, comprising a further step, after the step ofremoving the second layer, of selectively removing the first layer.
 7. Amethod for manufacturing a semiconductor device as defined in claim 5,comprising further steps, after the step of forming a groove by etchingthe semiconductor substrate, of:processing an inside wall of the grooveby means of a chemical dry etching process; and annealing the insidewall of the groove processed by the chemical dry etching process.
 8. Amethod for manufacturing a semiconductor device as defined in claim 5,comprising a step, before the step of forming an insulating film on aninside wall of the groove, of covering an end face of the first layerexposed inside the opening with an oxidation-resisting film.
 9. A methodfor manufacturing a semiconductor device comprising steps of:depositingin order a first layer and a second layer on a main surface of an SOIlayer set on an insulating substrate; forming an opening in the firstlayer and the second layer exposing a portion of the main surface of theSOI layer; forming an isolation trench reaching through to theinsulating substrate by etching the SOI layer through the opening usingthe second layer as a mask; forming an insulating film on an inside wallof the isolation trench, the insulating film being a material differentfrom a material of the first layer; filling the isolation trench with afiller through the opening until a top surface of the filler becomesequal to or higher than the first layer in height and so that the fillercontacts the first layer at the opening; and removing the second layerusing the filler and the first layer as an etching stopper to preventthe insulating film located below a contact portion between the firstlayer and the filler from being etched during the removal of the secondlayer.
 10. A method for manufacturing a semiconductor device as definedin claim 9, comprising a further step, after the step of removing thesecond layer, of selectively removing the first layer.
 11. A method formanufacturing a semiconductor device as defined in claim 9, comprisingfurther steps, after the step of forming an isolation trench,of:processing an inside wall of the isolation trench by means of achemical dry etching process; and annealing the inside wall of theisolation trench processed by the chemical dry etching process.
 12. Amethod for manufacturing a semiconductor device comprising stepsof:depositing in order a first layer and a second layer on a mainsurface of an SOI layer set on an insulating substrate; forming anopening in the first layer and the second layer exposing a portion ofthe main surface of the SOI layer; forming an isolation trench reachingthrough to the insulating substrate by etching the SOI layer through theopening using the second layer as a mask; covering an end face of thefirst layer exposed inside the opening with an oxidation-resisting film;forming an insulating film on an inside wall of the isolation trench;filling the isolation trench with a filler through the opening until atop surface of the filler becomes equal to or higher than the firstlayer in height; and removing the second layer using the filler and thefirst layer as an etching stopper.
 13. A method for manufacturing asemiconductor device comprising steps of:forming a field oxide filmhaving a thick portion and a thin portion, a silicon nitride film, and asilicon oxide film to be used as a mask, in order, on a main surface ofa silicon substrate; forming an opening in the thick portion of thefield oxide film by selectively etching the thick portion of the fieldoxide film, the silicon nitride film, and the silicon oxide film;forming a groove by etching the silicon substrate through the openingusing the silicon oxide film as a mask; forming an insulating film on aninside wall of the groove; filling the groove with polysilicon; etchingback the polysilicon deposited on the silicon oxide film by controllingthe etching so that a top surface of the polysilicon in the groovebecomes higher than a top surface of the silicon nitride film; andetching off the silicon oxide film using the polysilicon in the grooveand the silicon nitride film as an etching stopper for the field oxidefilm and the insulating film.
 14. A method for manufacturing asemiconductor device comprising:forming a field oxide film having athick portion and a thin portion, a polysilicon film, and a siliconoxide film to be used as a mask, in order, on a main surface of asilicon substrate; forming an opening in the thick portion of the fieldoxide film by selectively etching the thick portion of the field oxidefilm, the polysilicon film, and the silicon oxide film; covering thepolysilicon film exposed on a surface of a wall of the opening with anoxidation-resisting film; forming a groove by etching the siliconsubstrate from the opening using the silicon oxide film as a mask;forming an insulating film on an inside wall of the groove; filling thegroove with polysilicon for filling; etching back the polysilicon forfilling deposited on the silicon oxide film while controlling theetching so that a top surface of the polysilicon for filling in thegroove becomes higher than a top surface of the polysilicon film; andetching off the silicon oxide film using the polysilicon for filling inthe groove and the polysilicon film as an etching stopper for the fieldoxide film and the insulating film.
 15. A method for manufacturing asemiconductor device according to claim 5, wherein the first layer is asilicon nitride film, the second layer is a silicon oxide film, and theinsulating film is a silicon oxide film.
 16. A method for manufacturinga semiconductor device according to claim 15, wherein the filler ispolycrystalline silicon.
 17. A method for manufacturing a semiconductordevice according to claim 6, wherein the first layer is a siliconnitride film, the second layer is a silicon oxide film, and theinsulating film is a silicon oxide film.
 18. A method for manufacturinga semiconductor device according to claim 17, wherein the filler ispolycrystalline silicon.
 19. A method for manufacturing a semiconductordevice according to claim 7, wherein the first layer is a siliconnitride film, the second layer is a silicon oxide film, and theinsulating film is a silicon oxide film.
 20. A method for manufacturinga semiconductor device according to claim 19, wherein the filler ispolycrystalline silicon.
 21. A method for manufacturing a semiconductordevice according to claim 9, wherein the first layer is a siliconnitride film, the second layer is a silicon oxide film, and theinsulating film is a silicon oxide film.
 22. A method for manufacturinga semiconductor device according to claim 21, wherein the filler ispolycrystalline silicon.
 23. A method for manufacturing a semiconductordevice according to claim 10, wherein the first layer is a siliconnitride film, the second layer is a silicon oxide film, and theinsulating film is a silicon oxide film.
 24. A method for manufacturinga semiconductor device according to claim 23, wherein the filler ispolycrystalline silicon.
 25. A method for manufacturing a semiconductordevice according to claim 11, wherein the first layer is a siliconnitride film, the second layer is a silicon oxide film, and theinsulating film is a silicon oxide film.
 26. A method for manufacturinga semiconductor device according to claim 25, wherein the filler ispolycrystalline silicon.